VCC pump for CMOS imagers

ABSTRACT

A CMOS imaging device which includes a charge pump connected to one or more of a reset gate, transfer gate and row select gate of sensor cells and provides gate control signals which give the imaging device an increased dynamic range charge capacity while minimizing signal leakage. A charge pump may also supply control signals to photogates used in the cells.

FIELD OF THE INVENTION

The invention relates generally to improved semiconductor imagingdevices and in particular to an imaging device which can be fabricatedusing a standard CMOS process. Particularly, the invention relates to aCMOS imager having an array of image sensing cells and to the drivingsignals which operate the cells.

DISCUSSION OF RELATED ART

There are a number of different types of semiconductor-based imagers,including charge coupled devices (CCDs), photodiode arrays, chargeinjection devices and hybrid focal plan arrays. CCDs are often employedfor image acquisition and enjoy a number of advantages which makes itthe incumbent technology, particularly for small size imagingapplications. CCDs are also capable of large formats with small pixelsize and they employ low noise charge domain processing techniques.However, CCD imagers also suffer from a number of disadvantages. Forexample, they are susceptible to radiation damage, they exhibitdestructive read out over time, they require good light shielding toavoid image smear and they have a high power dissipation for largearrays. Additionally, while offering high performance, CCD arrays aredifficult to integrate with CMOS processing in part due to a differentprocessing technology and to their high capacitances, complicating theintegration of on-chip drive and signal processing electronics with theCCD array. While there has been some attempts to integrate on-chipsignal processing with the CCD array, these attempts have not beenentirely successful. CCDs also must transfer an image by line chargetransfers from pixel to pixel, requiring that the entire array be readout into a memory before individual pixels or groups of pixels can beaccessed and processed. This takes time, CCDs may also suffer fromincomplete charge transfer from pixel to pixel during charge transferwhich also results in image smear.

Because of the inherent limitations in CCD technology, there is aninterest in CMOS imagers for possible use as low cost imaging devices. Afully compatible CMOS sensor technology enabling a higher level ofintegration of an image array with associated processing circuits wouldbe beneficial to many digital applications such as, for example, incameras, scanners, machine vision systems, vehicle navigation systems,video telephones, computer input devices, surveillance systems, autofocus systems, star trackers, motion detection systems, imagestabilization systems and data compression systems for high-definitiontelevision.

The advantages of CMOS imagers over CCD imagers are that CMOS imagershave a low voltage operation and low power consumption; CMOS imagers arecompatible with integrated on-chip electronics (control logic andtiming, image processing, and signal conditioning such as A/Dconversion); CMOS imagers allow random access to the image data; andCMOS imagers have lower fabrication costs as compared with theconventional CCD since standard CMOS processing techniques can be used.Additionally, low power consumption is achieved for CMOS imagers becauseonly one row of pixels at a time needs to be active during the readoutand there is no charge transfer (and associated switching) from pixel topixel during image acquisition. On-chip integration of electronics isparticularly advantageous because of the potential to perform manysignal conditioning functions in the digital domain (versus analogsignal processing) as well as to achieve a reduction in system size andcost.

A CMOS imager circuit includes a focal plane array of pixel cells, eachone of the cells including either a photogate or a photodiode overlyinga substrate for accumulating photo-generated charge in the underlyingportion of the substrate. A readout circuit is connected to each pixelcell and includes at least an output field effect transistor formed inthe substrate and a charge transfer section formed on the substrateadjacent the photogate or photodiode having a sensing node, typically afloating diffusion node, connected to the gate of an output transistor.The imager may include at least one electronic device such as atransistor for transferring charge from the underlying portion of thesubstrate to the floating diffusion node and one device, also typicallya transistor, for resetting the node to a predetermined charge levelprior to charge transference.

In a CMOS imager, the active elements of a pixel cell perform thenecessary functions of: (1) photon to charge conversion; (2)accumulation of image charge; (3) transfer of charge to the floatingdiffusion node accompanied by charge amplification; (4) resetting thefloating diffusion node to a known state before the transfer of chargeto it; (5) selection of a pixel for readout; and (6) output andamplification of a signal representing pixel charge. Photo charge may beamplified when it moves from the initial charge accumulation region tothe floating diffusion node. The charge at the floating diffusion nodeis typically converted to a pixel output voltage by a source followeroutput transistor. The photosensitive element of a CMOS imager pixel istypically either a depleted p-n junction photodiode or a field induceddepletion region beneath a photogate. For photo diodes, image lag can beeliminated by completely depleting the photodiode upon readout.

CMOS imagers of the type discussed above are generally known asdiscussed, for example, in Nixon et al., “256×256 CMOS Active PixelSensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol.31(12) pp. 2046-2050, 1996; Mendis et al, “CMOS Active Pixel ImageSensors,” IEEE Transactions on Electron Devices, Vol. 41(3) pp. 452-453,1994 as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515,which are herein incorporated by reference.

To provide context for the invention, an exemplary CMOS imaging circuitis described below with reference to FIG. 1. The circuit describedbelow, for example, includes a photogate for accumulatingphoto-generated charge in an underlying portion of the substrate. Itshould be understood that the CMOS imager may include a photodiode orother image to charge converting device, in lieu of a photogate, as theinitial accumulator for photo-generated charge.

Reference is now made to FIG. 1 which shows a simplified circuit for apixel of an exemplary CMOS imager using a photogate and having a pixelphotodetector circuit 14 and a readout circuit 60. It should beunderstood that while FIG. 1 shows the circuitry for operation of asingle pixel, that in practical use there will be an M×N array of pixelsarranged in rows and columns with the pixels of the array accessed usingrow and column select circuitry, as described in more detail below.

The photodetector circuit 14 is shown in part as a cross-sectional viewof a semiconductor substrate 16 typically a p-type silicon, having asurface well of p-type material 20. An optional layer 18 of p-typematerial may be used if desired, but is not required. Substrate 16 maybe formed of, for example, Si, SiGe, Ge, and GaAs. Typically the entiresubstrate 16 is p-type doped silicon substrate and may contain a surfacep-well 20 (with layer 18 omitted), but many other options are possible,such as, for example p on p− substrates, p on p+ substrates, p-wells inn-type substrates or the like. The terms wafer or substrate used in thedescription includes any semiconductor-based structure having an exposedsurface in which to form the circuit structure used in the invention.Wafer and substrate are to be understood as including,silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a waferor substrate in the following description, previous process steps mayhave been utilized to form regions/junctions in the base semiconductorstructure or foundation.

An insulating layer 22 such as, for example, silicon dioxide is formedon the upper surface of p-well 20. The p-type layer may be a p-wellformed in substrate 16. A photogate 24 thin enough to pass radiantenergy or of a material which passes radiant energy is formed on theinsulating layer 22. The photogate 24 receives an applied control signalPG which causes the initial accumulation of pixel charges in n+ region26. The n+ type region 26, adjacent one side of photogate 24, is formedin the upper surface of p-well 20. A transfer gate 28 is formed oninsulating layer 22 between n+ type region 26 and a second n+ typeregion 30 formed in p-well 20. The n+ regions 26 and 30 and transfergate 28 form a charge transfer transistor 29 which is controlled by atransfer signal TX. The n+ region 30 is typically called a floatingdiffusion region. It is also a node for passing charge accumulatedthereat to the gate of a source follower transistor 36 described below.A reset gate 32 is also formed on insulating layer 22 adjacent andbetween n+ type region 30 and another n+ region 34 which is also formedin p-well 20. The reset gate 32 and n+ regions 30 and 34 form a resettransistor 31 which is controlled by a reset signal RST. The n+ typeregion 34 is coupled to voltage source VDD, e.g., 5 volts. The transferand reset transistor 29, 31 are n-channel transistors as described inthis implementation of a CMOS imager circuit in a p-well. It should beunderstood that it is possible to implement a CMOS imager in an n-wellin which case each of the transistors would be p-channel transistors. Itshould also be noted that while FIG. 1 shows the use of a transfer gate28 and associated transistor 29, this structure provides advantages, butis not required.

Photodetector circuit 14 also includes two additional n-channeltransistors, source follower transistor 36 and row select transistor 38.Transistors 36, 38 are coupled in series, source to drain, with thesource of transistor 36 also coupled over lead 40 to voltage source VDDand the drain of transistor 38 coupled to a lead 42. The drain of rowselect transistor 38 is connected via conductor 42 to the drains ofsimilar row select transistors for other pixels in a given pixel row. Aload transistor 39 is also coupled between the drain of transistor 38and a voltage source VSS, e.g. 0 volts. Transistor 39 is kept on by asignal VLN applied to its gate.

The imager includes a readout circuit 60 which includes a signal sampleand hold (S/H) circuit including a S/H n-channel field effect transistor62 and a signal storage capacitor 64 connected to the source followertransistor 36 through row transistor 38. The other side of the capacitor64 is connected to a source voltage VSS. The upper side of the capacitor64 is also connected to the gate of a p-channel output transistor 66.The drain of the output transistor 66 is connected through a columnselect transistor 68 to a signal sample output node VOUTS and through aload transistor 70 to the voltage supply VDD. A signal called “signalsample and hold” (SHS) briefly turns on the S/H transistor 62 after thecharge accumulated beneath the photogate electrode 24 has beentransferred to the floating diffusion node 30 and from there to thesource follower transistor 36 and through row select transistor 38 toline 42, so that the capacitor 64 stores a voltage representing theamount of charge previously accumulated beneath the photogate electrode24.

The readout circuit 60 also includes a reset sample and hold (S/H)circuit including a S/H transistor 72 and a signal storage capacitor 74connected through the S/H transistor 72 and through the row selecttransistor 38 to the source of the source follower transistor 36. Theother side of the capacitor 74 is connected to the source voltage VSS.The upper side of the capacitor 74 is also connected to the gate of ap-channel output transistor 76. The drain of the output transistor 76 isconnected through a p-channel column select transistor 78 to a resetsample output node VOUTR and through a load transistor 80 to the supplyvoltage VDD. A signal called “reset sample and hold” (SHR) briefly turnson the S/H transistor 72 immediately after the reset signal RST hascaused reset transistor 31 to turn on and reset the potential of thefloating diffusion node 30, so that the capacitor 74 stores the voltageto which the floating diffusion node 30 has been reset.

The readout circuit 60 provides correlated sampling of the potential ofthe floating diffusion node 30, first of the reset charge applied tonode 30 by reset transistor 31 and then of the stored charge from thephotogate 24. The two samplings of the diffusion node 30 charges producerespective output voltages VOUTR and VOUTS of the readout circuit 60.These voltages are then subtracted (VOUTS−VOUTR) by subtractor 82 toprovide an output signal terminal 81 which is an image signalindependent of pixel to pixel variations caused by fabricationvariations in the reset voltage transistor 31 which might cause pixel topixel variations in the output signal.

FIG. 2 illustrates a block diagram for a CMOS imager having a pixelarray 200 with each pixel cell being constructed in the manner shown byelement 14 of FIG. 1. FIG. 4 shows a 2×2 portion of pixel array 200.Pixel array 200 comprises a plurality of pixels arranged in apredetermined number of columns and rows. The pixels of each row inarray 200 are all turned on at the same time by a row select line, e.g.,line 86, and the pixels of each column are selectively output by acolumn select line, e.g., line 42. A plurality of rows and column linesare provided for the entire array 200. The row lines are selectivelyactivated by the row driver 210 in response to row address decoder 220and the column select lines are selectively activated by the columndriver 260 in response to column address decoder 270. Thus, a row andcolumn address is provided for each pixel. The CMOS imager is operatedby the control circuit 250 which controls address decoders 220, 270 forselecting the appropriate row and column lines for pixel readout, androw and column driver circuitry 210, 260 which apply driving voltage tothe drive transistors of the selected row and column lines.

FIG. 3 shows a simplified timing diagram for the signals used totransfer charge out of photodetector circuit 14 of the FIG. 1 CMOSimager. The photogate signal PG is nominally set to 5V and the resetsignal RST is nominally set at 2.5V. As can be seen from the figure, theprocess is begun at time t₀ by briefly pulsing reset voltage RST to 5V.The RST voltage, which is applied to the gate 32 of reset transistor 31,causes transistor 31 to turn on and the floating diffusion node 30 tocharge to the VDD voltage present at n+ region 34 (less the voltage dropVth of transistor 31). This resets the floating diffusion node 30 to apredetermined voltage (VDD−Vth). The charge on floating diffusion node30 is applied to the gate of the source follower transistor 36 tocontrol the current passing through transistor 38, which has been turnedon by a row select (ROW) signal, and load transistor 39. This current istranslated into a voltage on line 42 which is next sampled by providinga SHR signal to the S/H transistor 72 which charges capacitor 74 withthe source follower transistor output voltage on line 42 representingthe reset charge present at floating diffusion node 30. The PG signal isnext pulsed to 0 volts, causing charge to be collected in n+ region 26.A transfer gate voltage TX, similar to the reset pulse RST, is thenapplied to transfer gate 28 of transistor 29 to cause the charge in n+region 26 to transfer to floating diffusion node 30. It should beunderstood that for the case of a photogate, the transfer gate voltageTX may be pulsed or held to a fixed DC potential. For the implementationof a photodiode with a transfer gate, the transfer gate voltage TX mustbe pulsed. The new output voltage on line 42 generated by sourcefollower transistor 36 current is then sampled onto capacitor 64 byenabling the sample and hold switch 62 by signal SHS. The column selectsignal is next applied to transistors 68 and 70 and the respectivecharges stored in capacitors 64 and 74 are subtracted in subtractor 82to provide a pixel output signal at terminal 81.

It should also be noted that CMOS imagers may dispense with the transfergate 28 and associated transistor 29, or retain these structures whilebiasing the transfer transistor 29 to an always “on” state.

The operation of the charge collection of the CMOS imager is known inthe art and is described in several publications such as Mendis et al.,“Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172, pp. 19-291994; Mendis et al., “CMOS Active Pixel Image Sensors for HighlyIntegrated Imaging Systems,” IEEE Journal of Solid State Circuits, Vol.32(3), 1997; and Eric R, Fossum, “CMOS Image Sensors: Electronic Cameraon a Chip,” IEDM Vol. 95 pages 17-25 (1995) as well as otherpublications. These references are incorporated herein by reference.

Prior CMOS imagers suffer from inconsistent noise effects, voltage dropsand leakage across the reset transistor 31, the row select transistor 38and the transfer transistor 29. These affect the dynamic range of thepixel output as well as the ability of the pixel to accurately depict animage. Moreover, due to imprecision in the fabrication process, theelectrical properties of these transistors will vary from pixel to pixelcausing inconsistent output for the same level of charge from pixel topixel. Since the size of the pixel electrical signal is very small dueto the collection of photons in the photo array, the signal to noiseratio of the pixel should be as high as possible and charge leakagewithin a pixel as low as possible. Moreover, pixel output and theleakage of charge must be as consistent as possible from pixel to pixel.

SUMMARY OF THE INVENTION

The present invention is designed to improve variations in the resetvoltage and the leakage characteristics of a CMOS imager pixel whileimproving the consistency of the pixel to pixel output of the pixelarray and increasing the dynamic range of the pixel output. This isaccomplished by driving one or more of the reset gate, transfer gate (ifused) and the row select gate with one or more charge pumps. The chargepump provides a higher voltage than the supply voltage VDD to improvethe gating operation of the reset, transfer and row select transistors.The charge pump increases the voltage to the reset gate so that thevoltage drop across the reset transistor does not lower the VDD resetcharge at floating diffusion node 30 and increases the voltage to thetransfer gate to allow barrier and well lowering in its operation. Byoverdriving one or more of the gates of the reset, transfer and rowselect transistors with the output of a charge pump, pixel to pixelfabrication differences in electrical characteristics of thesetransistors can also be avoided. Moreover, if a photogate is used toacquire image charges this too may be overdriven by an output voltagefrom a charge pump. Since the photogate turn on voltage is typicallyVSS, e.g., 0 volts, a charge pump is used which drives the photogatewith an even lower voltage than VSS. Additionally, the photogate may beoverdriven, e.g. 6 volts, during charge collection to assure that chargeis effectively collected by the device.

The above and other advantages and features of the invention will bemore clearly understood from the following detailed description which isprovided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a representative circuit of the CMOS imager.

FIG. 2 is a block diagram of a CMOS active pixel sensor chip.

FIG. 3 is a representative timing diagram for the CMOS imager.

FIG. 4 is a representative pixel layout showing a 2×2 pixel layoutaccording to one embodiment of the present invention.

FIG. 5 is a representative circuit drawing of a charge pump that may beused with the present invention.

FIG. 6 is an illustration of a computer system having a CMOS imageraccording to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be described with reference to thefigures. Reference is now made to FIG. 4. This figure shows a portion ofan active pixel array constructed according to the present invention inwhich respective charge pumps 300, 301 and 302 are used to supply thegate voltages for the reset, transfer and row select transistors 31, 29and 38. In addition, a charge pumps 303 and 304 are shown for providinga gate voltage to a photogate 24 for charge transfer and charge storagerespectively. This figure shows a 2×2 array of pixels forsimplification. It should be understood that the invention is directedto a M×N multiple pixel array of any size.

The operation of the FIG. 4 pixel array will now be described.Photodetectors 14 of a row of pixels are coupled via their respectiverow select transistors 38 to column line 42. The photodetector selectedby a row decoder over line 86 will provide electrical current dependingupon the voltage at the gate of source follower transistor 36 suppliedby floating diffusion node 30. As noted, the gate of transistor 36controls the current through load transistor 39 (not shown in FIG. 4)and in consequence the voltage on lead 42.

Signal ROW SELECT1 on lead 86 turns row select transistor 38 on. Thevoltage controlled by the row select signal 86 is a charge pump 302output voltage. Row select 86 is connected to charge pump 302 tooverdrive the row select transistor, that is, the gate voltage oftransistor 38 is higher than the VDD supply voltage. In a 5V VDD system,charge pump 302 will supply at least VDD+Vth volts to the gate of rowselect transistor 38 where Vth is the threshold voltage for transistor38. The reset signal RST1 turns on transistor 31 which causes thefloating diffusion node 30 to be reset to a potential of VDD−Vth, whereVth is the threshold voltage of the reset transistor 31. In theinvention, the actual gate signal to transistor 31 is supplied by chargepump 300 to overdrive the gate of the reset transistor with a voltage ofat least the value VDD+Vth to maintain a constant voltage reset value onnode 30 at VDD. By having a higher reset voltage available at node 30, awider dynamic response range is available for the pixel output signaland variation in the voltage at which the floating diffusion node 30 isreset due to the reset transistor 31 Vth variation is reduced.

The photogate 24 is also supplied from a charge pump 304, ensuring thatthe photogate to be overdriven to its on state to ensure that allpossible collected charge for an image signal is stored in the imagersubstrate beneath the photogate until it is to be transferred out of thecollection area. The photogate 24 is also supplied from a charge pump303 in response to photogate signal PG over line 46, ensuring that thephotogate to be overdriven to its on state to ensure that all possiblecollected charge for an image signal is transferred from the substratebeneath the photogate to the collection area.

The FIG. 4 circuit shows use of a transfer gate 28 and associatedtransistor 29. If the CMOS imager cells uses a transfer transistor, thenthe transfer gate 28 voltage is also supplied from a charge pump 301 inresponse to transfer signal TX, once again ensuring that the transfertransistor is overdriven to its on state and eliminating the Vth voltagedrop which normally occurs. The operation of the FIG. 4 circuit toacquire, transfer and output pixel charge is otherwise as previouslydescribed.

In the invention, the charge pumps 300, 301 provide voltage to the resetgate 32 and transfer gate 28 at a potential which is greater than thesupply potential VDD. The pumped voltage enhances the performance of thetransfer and reset transistors. In order to turn “on” the varioustransistors of the pixel array, a gate voltage to the transistor mustexceed a source or drain voltage (depending on the type of transistor)by a threshold voltage Vth. However, the threshold voltage (Vth) maydiffer for each transistor of a pixel array due to manufacturingimperfections. As a consequence, when all transistors of the array areturned “on” or “off” using the voltage supply potentials to supplycontrol signals to the gates of the transistors, some transistors whichare turned “on” are more “on” than other transistors therebyinconsistently transferring and/or amplifying the pixel chargestransferred to the pixel output line 42. Likewise, some of thetransistors which are turned “off” are more “off” than other transistorscausing leakage. This is reflected as an improper output of signalsreflecting the charges collected by the photodetector circuit 14.

The charge pumps 300, 301, 302 and 304 help to overcome the inconsistenton/off threshold voltages (Vth) of the transistors by overdriving thegates with voltages which ensure that they turn on or off as required,regardless of manufacturing inconsistencies. Also, the charge pump 300increases the dynamic operating range of each pixel since the full resetvoltage VDD will be applied to the floating diffusion node 30. Thecharge pump 303 ensures that the maximum possible charges are collectedin the collection region beneath the photogate.

While multiple charge pumps 300, 301, 302, 303, 304 are shown in FIG. 4for the entire CMOS pixel array, it should be understood that a singlecharge pump having multiple controlled output voltages may be used forthe entire CMOS imager and for associated logic circuits. Also,individual charge pumps may be used for different portions of the imagercircuit and for the associated logic. Also, while the charge pumps 300,301, 302, 303, 304 are shown supplying voltage for the reset gate, thetransfer gate, the row select gate and the photogate, it should beunderstood that a charge pump may be used for one or more of these gatesto achieve a benefit over conventional CMOS imagers which do not use acharge pump.

Reference is now made to FIG. 5 which shows one exemplary charge pumpwhich may be used for one or more of charge pumps 300, 301, 302, 303 and304. Charge pumps, per se, are well known, such as those shown in U.S.Pat. No. 5,038,325 which is herein incorporated by reference. Theexemplary charge pump, shown in FIG. 5, uses two clamp circuits 320,330. An oscillator 310 provides its output to first and secondcapacitors 315, 335. Clamp circuits 320, 330 are connected across thecapacitors 315, 335. The oscillator 310 is a ring oscillator which canbe adjusted to increase or decrease its output signal frequency.

An output transistor 325 is connected between node 350 of capacitors 315and a circuit output 355 node. An input signal SIG, which might varybetween VDD and VSS, is output as an elevated potential signal SIGpwhich may vary between VSS and VDDp where VDDp>VDD. Where the potentialsignal SIGp is desired to be less than the operating voltage, i.e.,charge pump 303, the output signal SIGp which may vary between VSSp andVDD where VSSp<VSS.

Both clamp circuits 320, 330 turn on and off at the same time, but theconnection of clamp circuit 330 across capacitor 335 and in series withthe output transistor has the result that the operation of the secondclamp circuit 330 causes the output transistor 325 to conduct whenpotential at the node 350 is at a high potential. The rising edge of theoscillator 310 couples a high voltage through the capacitors 315, 335which shuts the clamps 320, 330 off and allows the nodes 350, 355 to gohigh. The falling edge of the output of the oscillator 310 couples adrop in potential through the capacitors 315, 335, at which point, theclamps 320, 330 turns on, preventing the nodes 350, 355 from going low.A decoupling capacitor 345 further cooperates with the charge pump 300in order to provide a steady boosted output which is switched by inputsignal SIG.

For operating the photogate PG, the charge pump 303 is configured tosupply an output voltage VSSp where VSSp<VSS. For collecting charge inthe photogate, the charge pump 304 is configured to supply an outputvoltage VPGp where VPGp is greater than input voltage VDD.

As noted, the particular construction of the charge pump is not criticalto the invention and many circuits besides the FIG. 5 circuit can beused. A representative output voltages of charge pumps 300, 301, 302,304 are 6.0, 6.0 and 6.0, respectively for a 5.0 volt VDD supply andassuming that the Vth of each of these transistors is less than 1.0volts. The charge pump 303 output has a representative voltage value of−1 volt. It should be understood that the output of voltage charge pumps300, 301, 302, 303 and 304 may vary, individually, depending upon theVDD and/or VSS supply as well as the Vth of the individual transistors.

A typical processor based system which includes a CMOS imager deviceaccording to the present invention is illustrated generally at 400 inFIG. 6. A processor based system is exemplary of a system having digitalcircuits which could include CMOS imager devices. Such a system couldinclude a computer system, camera system, scanner, machine visionsystem, vehicle navigation system, video phone, surveillance system,auto focus system, star tracker system, motion detection system, imagestabilization system and data compression system for high-definitiontelevision, all of which can utilize the present invention.

A processor system, such as a computer system, for example generallycomprises a central processing unit (CPU) 444 that communicates with aninput/output (I/O) device 446 over a bus 452. The CMOS imager 442 alsocommunicates with the system over bus 452. The computer system 400 alsoincludes random access memory (RAM) 448, and, in the case of a computersystem may include peripheral devices such as a floppy disk driver 454and a compact disk (CD) ROM drive 456 and I/O devices like a keyboardand/or mouse which also communicate with CPU 444 over the bus 452. CMOSimager 442 is preferably constructed as an integrated circuit whichincludes the voltage charge pumps 300, 301 and 302, as previouslydescribed with respect to FIGS. 4-7.

It should again be noted that although the invention has been describedwith specific reference to a CMOS imaging circuit having a photogate 24and a floating diffusion node 30, the invention has broaderapplicability and may be used in any CMOS imaging apparatus. Similarly,the process described above for charge collection, transfer and readoutis but one method of many that could be used. Accordingly, the abovedescription and accompanying drawings are only illustrative of preferredembodiments which can achieve the features and advantages of the presentinvention. It is not intended that the invention be limited to theembodiments shown and described in detail herein. The invention is onlylimited by the scope of the following claims.

1. An imaging device comprising: a photosensitive area within asubstrate for accumulating photo-generated charge in said area; areadout circuit comprising at least an output transistor formed in saidsubstrate; a controllable charge transfer region having a controlterminal, said transfer region being formed in said substrate adjacentsaid photosensitive area and having a node connected to a gate of saidoutput transistor and at least one charge transfer device fortransferring charge from said photosensitive area to said node inaccordance with a transfer control signal applied to said controlterminal; and a charge pump coupled to a supply voltage and connected tosupply said control signal to said charge transfer device.
 2. Theimaging device according to claim 1, wherein the accumulation of chargein said photosensitive area is conducted by a photogate.
 3. The imagingdevice according to claim 1, wherein said photosensitive area is aphotodiode.
 4. The imaging device according to claim 1, wherein saidcharge transfer device comprises a field effect transistor and saidcharge pump is connected to the gate of said field effect transistor. 5.The imaging device according to claim 1, wherein said node is a floatingdiffusion node.
 6. The imaging device according to claim 1, wherein theoutput of said charge pump is at a voltage greater than VDD, where VDDis a supply voltage.
 7. The imaging device according to claim 1, whereinthe output of said charge pump is at a voltage of at least VDD+Vth,where VDD is a supply voltage and Vth is a gate threshold voltage ofsaid charge transfer device.
 8. An imaging device comprising: aphotosensitive area within a substrate for accumulating photo-generatedcharge in said area; a readout circuit comprising at least an outputtransistor formed in said substrate; a controllable charge transferregion having a control terminal, said transfer region being formed insaid substrate adjacent said photosensitive area and having a nodeconnected to a gate of said output transistor and at least one chargetransfer device for transferring charge from said photosensitive area tosaid node in accordance with a transfer control signal applied to saidcontrol terminal; and a reset transistor responsive to a reset controlsignal for resetting said node to a predetermined charge condition priorto the transfer of charge thereto from said photosensitive area; and acharge pump coupled to a supply voltage and connected to supply saidreset control signal to said reset transistor.
 9. The imaging deviceaccording to claim 8, wherein the accumulation of charge in saidphotosensitive area is conducted by a photogate.
 10. The imaging deviceaccording to claim 8, wherein said photosensitive area is a photodiode.11. The imaging device according to claim 8, further comprising a nodeconnected to a gate of said output transistor and at least one chargetransfer device for transferring charge from said photosensitive area tosaid node in accordance with a transfer control signal applied to saidcontrol terminal.
 12. The imaging device according to claim 11, furthercomprising a charge pump coupled to a supply voltage and connected tosupply said control signal to said control transfer device.
 13. Theimaging device according to claim 11, wherein said charge transferregion is controlled by a field effect transistor.
 14. The imagingdevice according to claim 11, wherein said node is a floating diffusionnode.
 15. The imaging device according to claim 8, wherein the output ofsaid charge pump is at a voltage greater than VDD, where VDD is a supplyvoltage.
 16. The imaging device according to claim 8, wherein said resetdevice comprises a field effect transistor and said reset control signalis applied to a gate of said field effect transistor and the output ofsaid charge pump is at a voltage of at least VDD+Vth, where VDD is asupply voltage and Vth is a gate threshold voltage of said field effecttransistor.
 17. An imaging device comprising: a photosensitive areawithin a substrate for accumulating photo-generated charge in said area;a readout circuit comprising at least an output transistor formed insaid substrate; a charge transfer region being formed in said substrateadjacent said photosensitive area; a row select transistor for readingout a signal from said output transistor in response to a row selectsignal; and a charge pump coupled to a supply voltage and connected tosupply said row select signal to a gate of said row select transistor.18. The imaging device according to claim 17, wherein the accumulationof charge in said photosensitive area is conducted by a photogate. 19.The imaging device according to claim 17, wherein said photosensitivearea is a photodiode.
 20. The imaging device according to claim 17,further comprising a node connected to a gate of said output transistorand at least one charge transfer device for transferring charge fromsaid photosensitive area to said node in accordance with a transfercontrol signal applied to said control terminal.
 21. The imaging deviceaccording to claim 20, further comprising a charge pump coupled to asupply voltage and connected to supply said control signal to saidcontrol transfer device.
 22. The imaging device according to claim 20,wherein said charge transfer region is controlled by a field effecttransistor.
 23. The imaging device according to claim 20, wherein saidnode is a floating diffusion node.
 24. The imaging device according toclaim 17, wherein the output of said charge pump is at a voltage greaterthan VDD, where VDD is a supply voltage.
 25. The imaging deviceaccording to claim 17, wherein the output of said charge pump is at avoltage of at least VDD+Vth, where VDD is a supply voltage and Vth is agate threshold voltage of said row select transistor.
 26. An imagingdevice comprising: a photosensitive area within a substrate foraccumulating photo-generated charge in said area; a readout circuitcomprising at least an output transistor formed in said substrate; acontrollable charge transfer region having a control terminal, saidtransfer region being formed in said substrate adjacent saidphotosensitive area and having a node connected to a gate of said outputtransistor and at least one charge transfer device for transferringcharge from said photosensitive area to said node in accordance with atransfer control signal applied to said control terminal; a resettransistor responsive to a reset control signal for resetting said nodeto a predetermined charge condition prior to the transfer of chargethereto from said photosensitive area; a row select transistor forreading out a signal from said output transistor in response to a rowselect signal; a first charge pump coupled to a supply voltage andconnected to supply said control signal to said charge transfer device;a second charge pump coupled to a supply voltage and connected to supplysaid reset select signal to said reset transistor; and a third chargepump coupled to a supply voltage and connected to supply said row selectsignal to said row select transistor.
 27. The imaging device accordingto claim 26, wherein the accumulation of charge in said photosensitivearea is conducted by a photogate.
 28. The imaging device according toclaim 27, further comprising a fourth charge pump coupled to a supplyvoltage and connected to supply a control signal to said photogate. 29.The imaging device according to claim 26, wherein said photosensitivearea is a photodiode.
 30. The imaging device according to claim 26,wherein said charge transfer region is controlled by a field effecttransistor.
 31. The imaging device according to claim 26, wherein saidnode is a floating diffusion node.
 32. The imaging device according toclaim 26, wherein the output of said charge pump is at a voltage greaterthan VDD, where VDD is a supply voltage.
 33. The imaging deviceaccording to claim 26, wherein the output of said charge pumps are at avoltage of at least VDD+Vth, where VDD is a supply voltage and Vth is agate threshold voltage of said respective transistors.
 34. An imagingdevice comprising: a photosensitive device formed in a substrate foraccumulating photo-generated charge in said substrate; a readout circuitcomprising at least an output transistor formed in said substrate; acontrollable charge transfer region having a control terminal, saidtransfer region being formed in said substrate adjacent saidphotosensitive area and having a node connected to a gate of said outputtransistor and at least one charge transfer device for transferringcharge from said photosensitive area to said node in accordance with atransfer control signal applied to said control terminal; a resettransistor responsive to a reset control signal for resetting said nodeto a predetermined charge condition prior to the transfer of chargethereto from said photosensitive area; a row select transistor forreading out a signal from said output transistor in response to a rowselect signal; and a charge pump connected to a supply voltage andsupplying a voltage to at least said charge transfer device in responseto a charge transfer control signal.
 35. The imaging device according toclaim 34, wherein said photosensitive device is a photogate.
 36. Theimaging device according to claim 34, wherein said photosensitive deviceis a photodiode.
 37. The imaging device according to claim 34, whereinsaid charge transfer device comprises a field effect transistor and saidcharge pump is connected to the gate of said field effect transistor.38. The imaging device according to claim 34, further comprising acharge pump coupled to a supply voltage and connected to control saidrow select transistor in response to a row select control signal. 39.The imaging device according to claim 34, further comprising a chargepump coupled to a supply voltage and connected to control said resettransistor in response to a reset control signal.
 40. The imaging deviceaccording to claim 34, further comprising a charge pump coupled to asupply voltage and connected to control said reset transistor inresponse to a reset control signal; and a charge pump coupled to asupply voltage and connected to control said row select transistor inresponse to a row select signal.
 41. An imaging device comprising: aphotosensitive area within a substrate for accumulating photo-generatedcharge in said area; a photogate formed over said photosensitive area; areadout circuit in said substrate for supplying an output signalrepresenting charge accumulated in said photosensitive area; and a firstcharge pump coupled to a supply voltage and connected to supply a firstphotogate control signal to said photogate.
 42. The imaging deviceaccording to claim 41, further comprising: a charge transfer regionformed in said substrate adjacent said photosensitive area for receivingcharge transferred from said photosensitive area; and a reset transistorresponsive to a reset control signal for resetting said charge transferregion to a predetermined charge condition prior to the transfer ofcharge thereto from said photosensitive area.
 43. The imaging deviceaccording to claim 41 wherein said readout circuit comprises an outputtransistor, said image device further comprising a node connected to agate of said output transistor and at least one charge transfer devicefor transferring charge from said photosensitive area to said node inaccordance with a transfer control signal applied to said controlterminal.
 44. The imaging device according to claim 43, wherein saidcharge transfer region is controlled by a field effect transistor. 45.The imaging device according to claim 43, wherein said node is afloating diffusion node.
 46. The imaging device according to claim 41,wherein the output of said first charge pump is a voltage of VSSp whichis lower than a supply voltage VSS.
 47. The imaging device according toclaim 41, further comprising a second charge pump coupled to a supplyvoltage and connected to supply a second photogate control signal tosaid photogate.
 48. The imaging device according to claim 47, whereinsaid first photogate control signal instructs the photogate toaccumulate charge and said second photogate control signal instructs thephotogate to transfer charge.
 49. The imaging device according to claim47, wherein the output of said second charge pump is at a voltagegreater than VDD, where VDD is a supply voltage.
 50. The imaging deviceaccording to claim 47, wherein the output of said second charge pump isat a voltage of at least VDD+Vth, where VDD is a supply voltage and Vthis a gate threshold voltage of said photogate.
 51. The imaging deviceaccording to claim 50, wherein the output of said first charge pump is avoltage of VSSp which is lower than a supply voltage VSS.
 52. A methodfor generating an output signal corresponding to an image received by asensor on an array having rows and columns of pixel cells formed in asubstrate, each cell being capable of collecting electrical charge basedon a detected light intensity and having a diffusion node in saidsubstrate capable of holding an electrical charge, the method comprisingthe steps of: resetting the voltage of the respective diffusion nodes ofthe cells to a predetermined voltage; detecting a first reset voltage atrespective diffusion nodes of the cells; transferring electrical chargescollected at respective photoregions of the cells to respectivediffusion nodes using respective transistors which are controlled by asignal supplied from a charge pump; detecting a second voltage atrespective diffusion nodes of said cells; and generating respective celloutput signals from said detected first and second voltage of saidcells.
 53. The method for generating an output signal according to claim52, wherein said photoregion is a photogate.
 54. The method forgenerating an output signal according to claim 52, wherein saidphotoregion is a photodiode.
 55. The method for generating an outputsignal according to claim 52, wherein said reset transistor forresetting the voltage of said diffusion node is connected to a chargepump.
 56. The method for generating an output signal according to claim52, wherein said diffusion node is a floating diffusion node.
 57. Amethod for generating an output signal corresponding to an imagereceived by a sensor array having rows and columns of pixel cells formedin a substrate, each cell being capable of collecting electrical chargebased on a detected light intensity and having a diffusion node in saidsubstrate capable of holding an amount of electrical charge, the methodcomprising the steps of: resetting the voltage of the respectivediffusion nodes of the cells to a predetermined voltage, wherein saidvoltage is reset by a respective reset transistor which is controlled bya reset signal supplied by a charge pump; detecting a first resetvoltage at respective diffusion nodes of the cells; transferringelectrical charges collected at respective photoregions of the cells torespective diffusion nodes; detecting a second voltage at respectivediffusions node of said cells; and generating cell output signals fromsaid detected first and second voltages of said cells.
 58. The methodfor generating an output signal according to claim 57, wherein saidphotoregion is a photogate.
 59. The method for generating an outputsignal according to claim 57, wherein said photoregion is a photodiode.60. The method for generating an output signal according to claim 57,wherein said diffusion nodes are reset by a reset transistor operated bya charge pump.
 61. The method for generating an output signal accordingto claim 57, wherein said diffusion node is a floating diffusion node.62. The method for generating an output signal according to claim 58,wherein said photogate is activated by a signal coupled to a chargepump.
 63. The method for generating an output signal according to claim57, wherein said electrical charge is transferred by respective cellcharge transfer devices coupled to a charge transfer signal provided bya charge pump.
 64. The method for generating an output signalcorresponding to an image received by a sensor array having rows andcolumns of pixel cells formed in a substrate, each cell being capable ofcollecting electrical charge based on a detected light intensity andhaving a diffusion node in said substrate capable of holding an amountof electrical charge, the method comprising the steps of: resetting thevoltage of the respective diffusion nodes of the cells to apredetermined voltage, wherein said voltage is reset by respective resettransistors which is operated by a reset signal supplied by a firstvoltage pump; detecting a first voltage at respective diffusion nodes ofthe cells; transferring electrical charges collected at respectivephotoregions of the cells to said diffusion nodes using respectivetransistors which are controlled by a transfer signal supplied by asecond charge pump; detecting a second voltage at the respectivediffusion nodes of said cells; and generating cell output signals fromsaid detected first and second voltages of said cells.
 65. The methodfor generating an output signal according to claim 64, wherein saidphotoregion is a photogate.
 66. The method for generating an outputsignal according to claim 64, wherein said photoregion is a photodiode.67. The method for generating an output signal according to claim 64,wherein said transistors for resetting the voltage of respectivediffusion nodes and said transistors for transferring charge to saiddiffusion nodes are connected to a first and a second charge pumprespectively, each of which provides a respective supply voltage of atleast VDD+Vth, wherein VDD is a supply voltage and Vth is a gatethreshold voltage of the respective reset and transfer transistors. 68.The method for generating an output signal according to claim 64,wherein said diffusion node is a floating diffusion node.
 69. An imagingsystem for generating output signals based on a received image, theimaging system comprising: a plurality of active pixel cells arrangedinto an array of rows and columns, each active pixel cell being operableto generate a voltage at a diffusion node corresponding to detectedlight intensity by the cells, each of said cells including a resetdevice for resetting a voltage at said diffusion node, a transfer devicefor transferring charge from a photosensitive area to said diffusionnode and a row select device for reading out a signal representingcharges at said diffusion node; at least one voltage pump coupled to asupply voltage and connected to at least one of a reset device, atransfer device and a row select device of said cells to effectivelyoperate said devices in response to respective control signals; a rowdecoder having a plurality of row lines connected to the array, each rowline being connected to the row select devices for cells in a particularrow of said array; and a column decoder having a plurality of columncontrol lines connected to the array for selecting and outputting pixeloutput signals whereby pixels of the array are selected for output byrow address and column address.
 70. The imaging system according toclaim 69, wherein said active pixel cells each include a photogate atsaid photosensitive area.
 71. The imaging system according to claim 68,wherein the photogates of said cells is connected to a voltage pumpwhich provides a photogate signal to said photogates.
 72. The imagingsystem according to claim 69, wherein said active pixel cells eachinclude a photodiode at said photosensitive area.
 73. The imaging systemof claim 69, wherein said reset devices are connected to a voltage pumpwhich provides a reset signal to said reset devices.
 74. The imagingsystem of claim 69, wherein said transfer devices are connected to avoltage pump which provides transfer signal to said transfer devices.75. The imaging system of claim 69, wherein said row select devices areconnected to a voltage pump which provides row select signal to said rowselect devices.
 76. The imaging device according to claim 69, whereinthe output of said charge pump is at a voltage greater than VDD, whereVDD is a supply voltage.
 77. The imaging system according to claim 69,wherein said reset device, said transfer device and said row selectdevice are connected to at least one charge pump which provides a chargepump voltage of at least VDD+Vth, wherein VDD is a supply voltage andVth is a gate threshold voltage.
 78. The imaging system according toclaim 69, wherein said diffusion node is a floating diffusion node. 79.An imaging system comprising: (i) a processor; and (ii) a CMOS imagingdevice for supplying image signals to said processor, said CMOS imagingdevice comprising: a photosensitive area within a substrate foraccumulating photo-generated charge in said area; a readout circuitcomprising at least an output transistor formed in said substrate; acontrollable charge transfer region having a control terminal, saidtransfer region being formed in said substrate adjacent saidphotosensitive area and having a node connected to a gate of said outputtransistor and at least one charge transfer device for transferringcharge from said photosensitive area to said node in accordance with atransfer control signal applied to said control terminal; and a chargepump coupled to a supply voltage and connected to supply said controlsignal to said charge transfer device.
 80. The system according to claim79, wherein the accumulation of charge in said photosensitive area isconducted by a photogate.
 81. The system according to claim 79, whereinsaid photosensitive area is a photodiode.
 82. The system according toclaim 79, wherein said node is a floating diffusion node.
 83. The systemaccording to claim 79, wherein said system is a camera system.
 84. Thesystem according to claim 79, wherein said system is a scanner.
 85. Thesystem according to claim 79, wherein said system is a machine visionsystem.
 86. The system according to claim 79, wherein said system is avehicle navigation system.
 87. The system according to claim 79, whereinsaid system is a video telephone system.
 88. An imaging systemcomprising: (i) a processor; and (ii) a CMOS imaging device forsupplying image signals to said processor, said CMOS imaging devicecomprising: a photosensitive area within a substrate for accumulatingphoto-generated charge in said area; a readout circuit comprising atleast an output transistor formed in said substrate; a controllablecharge transfer region having a control terminal, said transfer regionbeing formed in said substrate adjacent said photosensitive area andhaving a node connected to a gate of said output transistor and at leastone charge transfer device for transferring charge from saidphotosensitive area to said node in accordance with a transfer controlsignal applied to said control terminal; a reset transistor responsiveto a reset control signal for resetting said node to a predeterminedcharge condition prior to the transfer of charge thereto from saidphotosensitive area; and a charge pump coupled to a supply voltage andconnected to supply said reset control signal to said reset device. 89.The system according to claim 88, wherein the accumulation of charge insaid photosensitive area is conducted by a photogate.
 90. The systemaccording to claim 88, wherein said photosensitive area is a photodiode.91. The system according to claim 88, wherein said node is a floatingdiffusion node.
 92. The system according to claim 88, wherein saidsystem is a camera system.
 93. The system according to claim 88, whereinsaid system is a scanner.
 94. The system according to claim 88, whereinsaid system is a machine vision system.
 95. The system according toclaim 88, wherein said system is a vehicle navigation system.
 96. Thesystem according to claim 88, wherein said system is a video telephonesystem.
 97. An imaging system comprising: (i) a processor; and (ii) aCMOS imaging device for supplying image signals to said processor, saidCMOS imaging device comprising: a photosensitive area within a substratefor accumulating photo-generated charge in said area; a readout circuitcomprising at least an output transistor formed in said substrate; acontrollable charge transfer region having a control terminal, saidtransfer region being formed in said substrate adjacent saidphotosensitive area and having a node connected to a gate of said outputtransistor and at least one charge transfer device for transferringcharge from said photosensitive area to said node in accordance with atransfer control signal applied to said control terminal; a row selecttransistor for reading out a signal from said output transistor inresponse to a row select signal; and a charge pump coupled to a supplyvoltage and connected to supply said row select signal to said rowselect transistor.
 98. The system according to claim 97, furthercomprising a second charge pump coupled to a supply voltage andconnected to supply said transfer control signal to said change transferdevice.
 99. The system according to claim 97, further comprising a resettransistor to reset said node, wherein the gate of said reset transistoris coupled to the output of a third charge pump to supply a reset signalto the gate of said reset transistor.
 100. The system according to claim97, wherein the accumulation of charge in said photosensitive area isconducted by a photogate connected to a fourth charge pump whichprovides a photogate signal to said photogate.
 101. The system accordingto claim 100, further comprising a fifth charge pump coupled to a supplyvoltage and connected to said photogate to supply an elevated outputvoltage to increase charge collection in said photogate.
 102. The systemaccording to claim 101, wherein the output of said fifth charge pump isat a voltage greater than VDD, where VDD is a supply voltage.
 103. Thesystem according to claim 101, wherein the output of said fifth chargepump is at a voltage of at least VDD+Vth, where VDD is a supply voltageand Vth is a gate threshold voltage of said photogate.
 104. The systemaccording to claim 97, wherein the accumulation of charge in saidphotosensitive area is conducted by a photogate.
 105. The systemaccording to claim 97, wherein said photosensitive area is a photodiode.106. The system according to claim 97, wherein said charge transferdevice is controlled by a field effect transistor and said charge pumpis connected to the gate of said transistor.
 107. The system accordingto claim 97, wherein said node is a floating diffusion node.
 108. Thesystem according to claim 97, wherein said system is a camera system.109. The system according to claim 97, wherein said system is a scanner.110. The system according to claim 97, wherein said system is a machinevision system.
 111. The system according to claim 97, wherein saidsystem is a vehicle navigation system.
 112. The system according toclaim 97, wherein said system is a video telephone system.
 113. A pixelfor an imaging device comprising: a photosensitive device providedwithin a substrate for providing photo-generated charges; a circuitassociated with said photosensitive device for providing at least onepixel output signal representative of said photo-generated charges, saidcircuit including at least a first operative device that is responsiveto a control signal during operation of said associated circuit; and afirst charge pump responsive to an applied control signal for supplyinga first pumped voltage signal to said first operative device.
 114. Thepixel of claim 113, wherein said first operative device is a resetdevice and said first pumped voltage signal is used to reset a portionof said pixel to a predetermined state.
 115. The pixel of claim 114,wherein said portion receives charges provided by said photosensitivedevice.
 116. The pixel of claim 113, wherein said first operative deviceis a row select device and said first pumped voltage signal is used tooutput a signal representing charges provided by said photosensitivedevice.
 117. The pixel of claim 113, wherein said first operative deviceis a transistor.
 118. The pixel of claim 113, wherein said associatedcircuit further comprises: a second operative device that is responsiveto a control signal during operation of said associated circuit; and asecond charge pump responsive to an applied control signal for supplyinga second pumped voltage signal to said second operative device.
 119. Thepixel of claim 118, wherein said first operative device is a resetdevice, said first pumped voltage signal is used to reset a portion ofsaid pixel to a predetermined state, said second operative device is arow select device and said second pumped voltage signal is used tooutput a signal representing charges provided by said photosensitivedevice.
 120. The pixel of claim 119, wherein said portion receivescharges provided by said photosensitive device.
 121. The pixel of claim118, wherein said first and second operative devices are transistors.122. A pixel for an imaging device comprising: a charge storage areawithin a substrate for storing photo-generated charge; a firsttransistor electrically coupled to said charge storage area, said firsttransistor being responsive to a first control signal; and a firstcharge pump for supplying said first control signal to said firsttransistor, wherein said first transistor is a reset transistor and saidfirst control signal is used to reset said charge storage area.
 123. Apixel for an imaging device comprising: a charge storage area within asubstrate for storing photo-generated charge; a first transistorelectrically coupled to said charge storage area, said first transistorbeing responsive to a first control signal; and a first charge pump forsupplying said first control signal to said first transistor, whereinsaid first transistor is a row select transistor for outputting a signalrepresenting charge stored in said charge storage area, and said firstcontrol signal is used to control the output of said signal.
 124. Apixel for an imaging device comprising: a charge storage area within asubstrate for storing photo-generated charge; a first transistorelectrically coupled to said charge storage area, said first transistorbeing responsive to a first control signal; a first charge pump forsupplying said first control signal to said first transistor; a secondtransistor electrically coupled to receive a signal representing storedcharge in said area, said second transistor being responsive to a secondcontrol signal; and a second charge pump for supplying said secondcontrol signal to said second transistor.
 125. The pixel of claim 124,wherein said first transistor is a reset transistor, said first controlsignal is used to reset said storage area, said second transistor is arow select transistor and said second control signal is used to output asignal representing stored charge in said charge storage area.
 126. Apixel for an imaging device comprising: a charge storage area within asubstrate for storing photo-generated charge; a first transistorelectrically coupled to said charge storage area, said first transistorbeing responsive to a first control signal; and a first charge pump forsupplying said first control signal to said first transistor, whereinsaid charge storage area receives charge transferred from a photoconversion device.
 127. An imaging device comprising: a photosensitivearea within a substrate for accumulating photo-generated charge in saidarea; a readout transistor electrically coupled to said photosensitivearea, said readout transistor supplying an output signal representingcharge accumulated in said photosensitive area; a row select transistorfor reading out the output signal from said readout transistor inresponse to a row select signal; and a first voltage pump for supplyingsaid row select signal to said row select transistor.
 128. The imagingdevice of claim 127, further comprising: a photogate formed over saidphotosensitive area, said photogate being responsive to a firstphotogate control signal to accumulate charge in said photosensitivearea; and a second voltage pump for supplying said first photogatecontrol signal to said photogate.
 129. The imaging device of claim 128,wherein said photogate is responsive to a second photogate controlsignal and said imaging device further comprises a third voltage pumpfor supplying said second photogate control signal to said photogate.130. The imaging device of claim 128 further comprising: a resettransistor responsive to a reset control signal for resetting an areacontaining charges accumulated by said photosensitive area; and a thirdvoltage pump for supplying said reset control signal to said resettransistor.
 131. An imaging device comprising: a photosensitive areawithin a substrate for accumulating photo-generated charge in said area;a readout circuit for supplying an output signal representing chargeaccumulated in said photosensitive area; a reset transistor responsiveto a reset control signal for resetting an area containing chargesaccumulated in said photosensitive area; and a first voltage pump forsupplying said reset control signal to said reset transistor.
 132. Theimaging device of claim 131, further comprising: a row select transistorfor reading out the output signal from said readout circuit in responseto a row select signal; and a second voltage pump for supplying said rowselect signal to said row select transistor.
 133. The imaging device ofclaim 131, further comprising: a photogate formed over saidphotosensitive area, said photogate being responsive to a firstphotogate control signal to accumulate charge in said photosensitivearea; and a second voltage pump for supplying said first photogatecontrol signal to said photogate.
 134. The imaging device of claim 133,wherein said photogate is responsive to a second photogate controlsignal and said imaging device further comprises a third voltage pumpfor supplying said second photogate control signal to said photogate.135. An imaging device comprising: a plurality of pixels arranged in anarray, each of said pixels comprising: a photosensitive device providedwithin a substrate for providing photo-generated charges; a circuitassociated with said photosensitive device for providing at least onepixel output signal representative of said photo-generated charges, saidcircuit including at least a first operative device that is responsiveto a control signal during operation of said associated circuit; and afirst charge pump responsive to an applied control signal for supplyinga first pumped voltage signal to said first operative device.
 136. Thedevice of claim 135, wherein said first operative device is a resetdevice and said first pumped voltage signal is used to reset a portionof said pixel to a predetermined state.
 137. The device of claim 136,wherein said portion receives charges provided by said photosensitivedevice.
 138. The device of claim 135, wherein said first operativedevice is a row select device and said first pumped voltage signal isused to output a signal representing charges provided by saidphotosensitive device.
 139. The device of claim 135, wherein said firstoperative device is a transistor.
 140. The device of claim 135, whereinsaid associated circuit further comprises: a second operative devicethat is responsive to a control signal during operation of saidassociated circuit; and a second charge pump responsive to an appliedcontrol signal for supplying a second pumped voltage signal to saidsecond operative device.
 141. The device of claim 140, wherein saidfirst operative device is a reset device, said first pumped voltagesignal is used to reset a portion of said pixel to a predeterminedstate, said second operative device is a row select device and saidsecond pumped voltage signal is used to output a signal representingcharges provided by said photosensitive device.
 142. The device of claim141, wherein said portion receives charges provided by saidphotosensitive device.
 143. The device of claim 140, wherein said firstand second operative devices are transistors.
 144. The device of claim140, wherein said associated circuit further comprises: a thirdoperative device that is responsive to a control signal during operationof said associated circuit; and a third charge pump responsive to anapplied control signal for supplying a third pumped voltage signal tosaid third operative device.
 145. An imaging system comprising: aprocessor; and an imaging device for supplying image signals to saidprocessor, said imaging device comprising a plurality of pixels arrangedin an array, each pixel comprises: a charge storage area within asubstrate for storing photo-generated charge, a first transistorelectrically coupled to said charge storage area, said first transistorbeing responsive to a first control signal, and a first charge pump forsupplying said first control signal to said first transistor.
 146. Thesystem of claim 145, wherein said first transistor is a reset transistorand said first control signal is used to reset said charge storage area.147. The system of claim 145, wherein said first transistor is a rowselect transistor for outputting a signal representing charge stored insaid charge storage area, and said first control signal is used tocontrol the output of said signal.
 148. The system of claim 145, whereineach pixel further comprises: a second transistor electrically coupledto receive a signal representing stored charge in said area, said secondtransistor being responsive to a second control signal; and a secondcharge pump for supplying said second control signal to said secondtransistor.
 149. The system of claim 148, wherein said first transistoris a reset transistor, said first control signal is used to reset saidstorage area, said second transistor is a row select transistor and saidsecond control signal is used to output a signal representing storedcharge in said charge storage area.
 150. The system of claim 145,wherein said charge storage area receives charge transferred from aphoto conversion device.
 151. An imaging system comprising: a processor;and an imaging device for supplying image signals to said processor,said imaging device comprising: a photosensitive area within a substratefor accumulating photo-generated charge in said area, a readouttransistor electrically coupled to said photosensitive area, saidreadout transistor supplying an output signal representing chargeaccumulated in said photosensitive area, a row select transistor forreading out the output signal from said readout transistor in responseto a row select signal, and a first voltage pump for supplying said rowselect signal to said row select transistor.
 152. The system of claim151, wherein said imaging device further comprises: a photogate formedover said photosensitive area, said photogate being responsive to afirst photogate control signal to accumulate charge in saidphotosensitive area; and a second voltage pump for supplying said firstphotogate control signal to said photogate.
 153. The system of claim152, wherein said photogate is responsive to a second photogate controlsignal and said imaging device further comprises a third voltage pumpfor supplying said second photogate control signal to said photogate.154. The system of claim 152, wherein said imaging device furthercomprises: a reset transistor responsive to a reset control signal forresetting an area containing charges accumulated by said photosensitivearea; and a third voltage pump for supplying said reset control signalto said reset transistor.
 155. An imaging system comprising: aprocessor; and an imaging device for supplying image signals to saidprocessor, said imaging device comprising: a photosensitive area withina substrate for accumulating photo-generated charge in said area, areadout circuit for supplying an output signal representing chargeaccumulated in said photosensitive area, a reset transistor responsiveto a reset control signal for resetting an area containing chargesaccumulated in said photosensitive area, and a first voltage pump forsupplying said reset control signal to said reset transistor.
 156. Thesystem of claim 155, wherein said imaging device further comprises: arow select transistor for reading out the output signal from saidreadout circuit in response to a row select signal; and a second voltagepump for supplying said row select signal to said row select transistor.157. The system of claim 155, wherein said imaging device furthercomprises: a photogate formed over said photosensitive area, saidphotogate being responsive to a first photogate control signal toaccumulate charge in said photosensitive area; and a second voltage pumpfor supplying said first photogate control signal to said photogate.158. The system of claim 157, wherein said photogate is responsive to asecond photogate control signal and said imaging device furthercomprises a third voltage pump for supplying said second photogatecontrol signal to said photogate.
 159. An imaging system comprising: aprocessor; and an imaging device for supplying image signals to saidprocessor, said imaging device comprising a plurality of pixels, each ofsaid pixels comprising: a photosensitive device provided within asubstrate for providing photo-generated charges, a circuit associatedwith said photosensitive device for providing at least one pixel outputsignal representative of said photo-generated charges, said circuitincluding at least a first operative device that is responsive to acontrol signal during operation of said associated circuit, and a firstcharge pump responsive to an applied control signal for supplying afirst pumped voltage signal to said first operative device.
 160. Amethod of generating an output signal corresponding to an image receivedby a sensor array having rows and columns of pixel cells formed in asubstrate, each cell being capable of collecting electrical charge basedon a detected light intensity and having a node in said substratecapable of holding an electrical charge, said method comprises:resetting the voltage of respective nodes of the cells to apredetermined voltage, said voltage being reset by respective resetdevices which are operated by a reset control voltage supplied by afirst voltage pump; detecting a first voltage at respective nodes of thecells; detecting a second voltage at the respective nodes of the cells;and generating cell output signals from the detected first and secondvoltages of the cells.
 161. A method of generating and outputting anoutput signal corresponding to an image received by a sensor arrayhaving rows and columns of pixel cells formed in a substrate, each cellbeing capable of collecting electrical charge based on a detected lightintensity and having a node in said substrate capable of holding anelectrical charge, said method comprises: resetting the voltage ofrespective nodes of the cells to a predetermined voltage; detecting afirst voltage at respective nodes of the cells; detecting a secondvoltage at the respective nodes of the cells; generating cell outputsignals from the detected first and second voltages of the cells; andoutputting the generated output signals using respective row selecttransistors responsive to respective row select control signals suppliedby a first voltage pump.